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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
FEATURES: DESCRIPTION:
IDT74AUC16374 ADVANCE INFORMATION
* ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * 1.8V Optimized * 0.8V to 2.7V Operating Range * Inputs/outputs tolerant up to 3.6V * Output drivers: 9mA @ 2.3V * Supports hot insertion * Available in TSSOP, TVSOP, and VFBGA packages
APPLICATIONS:
* high performance, low voltage communications systems * high performance, low voltage computing systems
This 16-bit edge-triggered D-type flip-flop is built using advanced CMOS technology. The AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VDD through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTIONAL BLOCK DIAGRAM
1OE 1CLK
2OE 2CLK
C1
1Q1 1D1 1D 2D1
C1
2Q1 1D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2003 Integrated Device Technology, Inc.
JANUARY 2003
DSC-6179/4
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PINOUT CONFIGURATION
6 1CLK
1D2 1D4 1D6 1D8 2D1 2D3 2D5 2D7 2CLK
5
NC
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
4
NC
GND
VDD
GND
GND
VDD
GND
NC
3
NC
GND
VDD
GND
GND
VDD
GND
NC
2
NC
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
1
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
A
B
C
D
E
VFBGA
F
G
H
J
K
NOTE: NC = No Internal Connection
56 BALL VFBGA PACKAGE LAYOUT
A 6 5 4 3 2 1
B
C
D
E
F
G
H
J
K
TOP VIEW 2
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Description Terminal Voltage with Respect to GND (all input and VDD terminals) VTERM Terminal Voltage with Respect to GND (any I/O or Output terminals in highimpedance or power-off state) TSTG IOUT IIK IOK IDD ISS Storage Temperature Continuous DC Output Current Continuous Clamp Current, VI < 0, or VI > VDD Continuous Clamp Current, VO < 0 Continuous Current through each VDD or GND -50 100 mA mA -65 to +150 20 50 C mA mA -0.5 to +3.6 V Max -0.5 to +3.6 Unit V
1OE 1Q1 1Q2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1CLK 1D1 1D2
GND
1Q3 1Q4
GND
1D3 1D4
VDD
1Q5 1Q6
VDD
1D5 1D6
GND
1Q7 1Q8 2Q1 2Q2
GND
1D7 1D8 2D1 2D2
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
2Q3 2Q4
GND
2D3 2D4
CAPACITANCE (TA = +25C, F = 1.0MHz, VDD = 2.5V)
Symbol CIN
(1)
Parameter Input Capacitance Output Capacitance Input Port Capacitance
Conditions VIN = 0V VOUT = 0V VIN = 0V
Typ. 3 5 3
Max.
Unit pF pF pF
VDD
2Q5 2Q6
VDD
2D5 2D6
COUT(2) CI(3)
GND
2Q7 2Q8 2OE
GND
2D7 2D8 2CLK
NOTES: 1. Applies to Control Inputs. 2. Applies to Data Outputs. 3. Applies to Data Inputs.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Inputs Output xDx H L X X xQx H L Q(2) Z xOE L L L H xCLK H or L X
TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names xDx xCLK xQx xOE Data Inputs Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW) Description
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition 2. Level of Q before the indicated steady-state conditions were established.
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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING CHARACTERISTICS(1)
Symbol VDD Parameter Supply Voltage VDD = 0.8V VDD = 1.1V to 1.3V VIH Input HIGH Voltage Level VDD = 1.4V to 1.6V VDD = 1.65V to 1.95V VDD = 2.3V to 2.7V VDD = 0.8V VDD = 1.1V to 1.3V VIL Input LOW Voltage Level VDD = 1.4V to 1.6V VDD = 1.65V to 1.95V VDD = 2.3V to 2.7V VI VO Input Voltage Output Voltage Active State 3-State VDD = 0.8V VDD = 1.1V IOH HIGH Level Output Current VDD = 1.4V VDD = 1.65V VDD = 2.3V VDD = 0.8V VDD = 1.1V IOL LOW Level Output Current VDD = 1.4V VDD = 1.65V VDD = 2.3V t/v TA Input Transition Rise or Fall Time Operating Free-Air Temperature Test Conditions Min. 0.8 VDD 0.65 x VDD 0.65 x VDD 0.65 x VDD 1.7 -- -- -- -- -- 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -40 Max. 2.7 -- -- -- -- -- 0 0.35 x VDD 0.35 x VDD 0.35 x VDD 0.7 2.7 VDD 2.7 -0.7 -3 -5 -8 -9 0.7 3 5 8 9 20 +85 ns/V C mA mA V V V V Unit V
NOTE: 1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)
Following Conditions Apply Unless Otherwise Specified: Operating Conditions: TA = -40C to +85C
Symbol IIH IIL IOFF IOZH IOZL IDDL IDDH IDDZ
NOTE: 1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.
Parameter Input HIGH or LOW Current All Inputs Input/Output Power Off Leakage High Impedance Output Current (3-State Output Pins) Quiescent Power Supply Current
Test Conditions VDD = 2.7V, VI = VDD or GND VDD = 0V, VIN or VO 2.7V VDD = 2.7V VDD = 0.8V to 2.7V VIN = GND or VDD VO = VDD VO = GND
Min. -- -- -- -- --
Typ. -- -- -- -- --
Max. 5 10 10 10 20
Unit A A A A
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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VDD = 0.8V - 2.7V IOH = -100A VDD = 0.8V IOH = -0.7mA IOH = -3mA VDD = 1.1V(2) IOH = -5mA VDD = 1.4V(3) (4) VDD = 1.65V IOH = -8mA VDD = 2.3V(5) IOH = -9mA VDD = 0.8V - 2.7V IOH = 100A VDD = 0.8V IOL = 0.7mA IOL = 3mA VDD = 1.1V(2) (3) IOL = 5mA VDD = 1.4V VDD = 1.65V(4) IOL = 8mA IOH = 9mA VDD = 2.3V(5) Min. VDD - 0.1 -- 0.8 1 1.2 1.8 -- -- -- -- -- -- Typ. -- 0.55 -- -- -- -- -- 0.25 -- -- -- -- Max. -- -- -- -- -- -- 0.2 -- 0.3 0.4 0.45 0.6 Unit
V
VOL
Output LOW Voltage
V
NOTES: 1. VIL and VIH must be within 2. Demonstrates operation for 3. Demonstrates operation for 4. Demonstrates operation for 5. Demonstrates operation for
the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS table for the appropriate VDD range. TA = -40C to +85C. nominal VDD = 1.2V. nominal VDD = 1.5V. nominal VDD = 1.8V. nominal VDD = 2.5V.
OPERATING CHARACTERISTICS, TA = 25C(1)
Symbol CPD (each output) CPD(Z) Parameter Power Dissipation Capacitance(2) Outputs Enabled, 1 Output Switching Power Dissipation Capacitance Outputs Disabled, 1 Clock and 1 Data Switching Power Dissipation Capacitance(3) Outputs Disabled, Clock Only Switching Test Conditions 1 fDATA = 5MHz 1 fCLK = 10MHz 1 fOUT = 5MHz OE = GND, CL = 0pF 1 fDATA = 5MHz 1 fCLK = 10MHz fOUT = not switching OE = VDD, CL = 0pF 1 fDATA = 0MHz 1 fCLK = 10MHz fOUT = not switching OE = VDD, CL = 0pF VDD = 0.8V VDD = 1.2V VDD = 1.5V VDD = 1.8V VDD = 2.5V Unit 24 24 24.1 26.2 31.2 pF
7.5
7.5
8
9.4
13.2
pF
CPD (each clock)
13.8
13.8
14
14.7
17.5
pF
NOTES: 1. Total device CPD for multiple (x) outputs switching and (n) clocks inputs switching = {x * CPD (each output)} + {n CPD (each clock)}. 2. CPD (each output). This is the CPD for each data bit where each input and output circuit is operating at 5MHz. The clock frequency is 10MHz and the numbers shown are minus the IDD component. 3. CPD (each clock); this is the CPD for each clock circuit, operating at 10MHz.
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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VDD = 0.8V VDD = 1.2V0.1V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ fCLOCK tSU tH tW Parameter Propagation Delay xCLK to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Clock Frequency Set-up Time, Data before CLK Hold Time, Data after CLK Pulse Duration, CLK HIGH or LOW Typ. 85 7.3 7 8.2 85 1.4 0.1 5.9 Min. -- 1 1.2 2 250 1 0.9 1.9 Max. 250 4.5 5.3 7.1 -- -- -- -- VDD = 1.5V0.1V Min. -- 0.8 0.8 1 250 1 0.9 1.9 Max. 250 2.9 3.6 4.8 -- -- -- -- VDD = 1.8V0.15V Min. -- 0.7 0.8 1.4 250 1 0.9 1.9 Typ. -- 1.5 1.5 2.7 -- -- -- -- Max. 250 2.8 2.9 4.5 -- -- -- -- VDD = 2.5V0.2V Min. -- 0.7 0.7 0.7 250 1 0.9 1.9 Max. 250 2.2 2.2 2.2 -- -- -- -- Unit MHz ns ns ns MHz ns ns ns
NOTE: 1. See TEST CIRCUITS AND WAVEFORMS. TA = -40C to +85C.
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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS(1)
Symbol VLOAD VT VLZ VHZ RL CL VDD = 0.8V 2xVDD VDD/2 100 100 2 15 VDD = 1.2V0.1V 2xVDD VDD/2 100 100 2 15 VDD = 1.5V0.1V 2xVDD VDD/2 100 100 2 15 VDD = 1.8V0.15V 2xVDD VDD/2 150 150 1 30 VDD = 2.5V0.2V 2xVDD VDD/2 150 150 0.5 30 Unit V V mV mV K pF
VDD RL Pulse Generator
(1)
VLOAD Open GND
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL
VIN D.U.T. RT
VOUT OPPOSITE PHASE INPUT TRANSITION
VDD VT 0V VOH VT VOL VDD VT 0V
CL
RL
Propagation Delay Test Circuits for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; slew rate 1V/ns.
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT
DISABLE
tPLZ
VDD VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
tPHZ VT 0V
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
VDD
LOW-HIGH-LOW PULSE tW
VT 0V
TIMING INPUT
VT 0V tSU tH VDD VT VT 0V
HIGH-LOW-HIGH PULSE
VDD VT
DATA INPUT
Pulse Width
Setup and Hold Times
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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX AUC Temp. Range X Bus- Hold XX Family XX XXX Device Type Package X Temp. I BV PA PF 374 16 Blank 74 Industrial Temperature Range Very Fine Pitch Ball Grid Array Thin Shrink Small Outline Package Thin Very Small Outline Package 16-Bit Edge-Triggered D-Type FlipFlop with 3-State Outputs Double-Density No bus-hold - 40C to +85C
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for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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